[Libre-soc-bugs] [Bug 382] nmigen wishbone Memory (SRAM) object needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=382

--- Comment #21 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #20)
> I started writing a L1 cache, you could probably use my code:
> https://git.libre-soc.org/?p=soc.git;a=tree;f=src/soc/memory_pipe_experiment;
> h=fa3eca3be8acf77bc31c680b54e56c08c5ef810b;hb=HEAD

the topic for this bugreport is specifically for an SRAM behind
a Wishbone interface.  strictly speaking, L1 cache design should
be discussed under a separate bugreport.

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