[Libre-soc-bugs] [Bug 417] FSM-based ALU example needed (compliant with ALU CompUnit)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=417

--- Comment #25 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #24)
> (In reply to Cesar Strauss from comment #23)
> 
> > I also sent a trimmed test case, without the shift state, which still
> > produces the issue.
> 

As it turns out, the behavior of cxxsim is consistent with it doing an implicit
Settle() after every yield. Your analysis on comment #15 helped narrow down
this anomaly in cxxsim.

The issue is not fixed yet, so I'd avoid relying on cxxsim results for the time
being.

> fantastic it came up in irc on freenode earlier

Interesting place. I joined the channel as "cesar".

-- 
You are receiving this mail because:
You are on the CC list for the bug.