[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #109 from Samuel A. Falvo II <kc5tja at arrl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #107)
> due to PowerISA numbering, this *might be largernumber:smallernumber
> and i do not know if that works as intended.
> 
>                 comb += expected_msr[MSR.TEs:MSR.TEe+1].eq(0)
> 
> 
> >>> l = [1,2,3,4]
> >>> l[2:0]
> []
> 
> it doesn't.  it returns an empty list.
> 
> MSR.TEs i believe is *greater* than TSR.TEe.
> 
>     TEs = (63 - 53)    # Trace Enable (subfield)
>     TEe = (63 - 54)    # Trace Enable (subfield)
> 
> >>> 63-53
> 10
> >>> 63-54
> 9
> 
> it is.  so that means that the above is:
> 
>             expected_msr[10:9+1]
> 
> which is going to be an empty list.
> 
> also in proof:
> 
> commit 64087f35f6b1e10429615836ec9077b55e8e85fd (HEAD -> master,
> origin/master)
> Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> Date:   Wed Jul 22 15:48:18 2020 +0100
> 
>     field number ordering wrong way round?

Then we're going to need a better abstraction for specifying arbitrary register
fields than just x[63-y].  This is perennial point of confusion, and I
guarantee anyone coming into the project will run into the same issues.

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