[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #24 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #23)
> >     spurious imports of FHDLTestCase, should be from nmutil
> 
>   Got it working.

excellent

> > generally, keeping "up-to-date" with absolute latest nmigen is inadviseable
> > without coordinating: it's a moving target.
> 
>   I totally agree. My update policy is to stick to a version as long
>   as it works. Then, when it do not, update to the newest possible.
>   So I make leaps between "very old" and "very new". Maybe I did miss
>   it but, I think you should keep track of the latest "compatible"
>   nMigen version, 

i am... except... well it's complicated, i am helping whitequark debug
cxxsim and also working on the processor: cxxsim should offer up to a *100*
times increase in simulation performance so is worth pursuing.

>   and maybe put it in a doc file at the root of the
>   soc repository. So this way people would quickly know which one
>   to install.

well i think we're good, now.  we did have a point where gtkwave wasn't
working, that i believe is fixed now.  and the spurious import is ok...
probably in the clear, now.

btw do do a "git pull" on soclayout, i just updated
non_generated/test_issuer.il

i have removed two read ports on the fast regfile which is so ridiculously
large (20% of the gate area) that it justified the effort.

these were reading the PC and the MSR (Machine Status Register) and i decided
to pass them as "immediates" to Branch and Trap, respectively, rather than
have the CompUnits read them a *second* time from *another* Fast Regfile port.

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