[Libre-soc-bugs] [Bug 417] FSM-based ALU example needed (compliant with ALU CompUnit)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=417

--- Comment #18 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
cesar: whitequark tells us that there should be no functional difference
between pysim and cxxsim.  therefore one is correct and one is not.

so no changes "if 1 sim d
type do this else do that" are appropriate.

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