[Libre-soc-bugs] [Bug 324] create POWER DIV pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #45 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #42)
> btw several combinatorial stages chained together is absolutely fine
> as long as it's not too many.  i'm going to try 8 (it's a 180nm ASIC)

Seems excessive since then there would be a gate depth of on the order of 100
per pipeline stage, I seriously doubt we can get any decent clock speed from
something *that* deep.

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