[Libre-soc-bugs] [Bug 502] determine SRAM block size and implement it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=502

Cole Poirier <colepoirier at gmail.com> changed:

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--- Comment #15 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Staf Verhaegen from comment #14)
> (In reply to Luke Kenneth Casson Leighton from comment #13)
> > okaay, here we go.  "make lvx" in soclayout experiments12
> > [snip]
> > this is what i was expecting: there is no Cell Library for yosys to
> > "understand" the block named SPBlock_512W6B48W.  how is that solved?
> 
> I can of think of some solutions:
> [snip]
> I think it is Jean-Paul who has to look at which solution is the best for
> his Coriolis flow.

I think this stackoverflow question and answer may provide the process needed
to do this:
https://stackoverflow.com/questions/60143268/how-to-create-a-custom-technology-cell-map-for-yosys

Note that Dave Shah has commented on the answer so it seems like it's the right
process.

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