[Libre-soc-bugs] [Bug 502] determine SRAM block size and implement it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=502

--- Comment #8 from Staf Verhaegen <staf at fibraservi.eu> ---
As asked in
http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001451.html
below is a generic SRAM simulation model in VHDL. I had to adapt the model for
multiple WE bits so the model is not fully tested. It does analyze with ghdl
though.

    -- Generic SRAM simulation model

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    entity sram is
      port (
        CLK:    in std_logic;
        -- Width of address will determine number of words in the RAM
        A:      in std_logic_vector;
        -- D and Q have to have the same width
        D:      in std_logic_vector;
        Q:      out std_logic_vector;
        -- Width of WE determines the write granularity
        WE:     in std_logic_vector
      );
    end entity sram;

    architecture rtl of sram is
      constant WEWORDBITS: integer := (D'length)/(WE'length);
      type word is array (WE'length - 1 downto 0) of
std_logic_vector(WEWORDBITS - 1 downto 0);
      type ram_type is array (0 to (2**A'length) - 1) of word;

      signal RAM:       ram_type;
      signal A_hold:    std_logic_vector(A'range);

      signal addr:      integer;
      signal addr_hold: integer;
    begin
      addr <= to_integer(unsigned(A));
      addr_hold <= to_integer(unsigned(A_hold));

      process(CLK) is
      begin
        if (rising_edge(CLK)) then
          A_hold <= A;
          for weword in 0 to WE'length - 1 loop
              if WE(weword) = '1' then
                -- Write cycle
                RAM(addr)(weword) <= D((weword + 1)*WEWORDBITS - 1 downto
weword*WEWORDBITS);
              end if;
          end loop;
        end if;
      end process;

      read: for weword in 0 to WE'length - 1 generate
      begin
        Q((weword + 1)*WEWORDBITS - 1 downto weword*WEWORDBITS) <=
RAM(addr_hold)(weword);
      end generate;
    end architecture rtl;

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