[Libre-soc-bugs] [Bug 76] IEEE754 RISC-V "tininess" as well as rounding modes (odd/even) needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=76

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   budget (EUR) for|1500                        |0
         this task,|                            |
          excluding|                            |
   subtasks' budget|                            |
         Resolution|---                         |INVALID
 total budget (EUR)|1500                        |0
  for completion of|                            |
       task and all|                            |
           subtasks|                            |
    parent task for|48                          |
  budget allocation|                            |
             Status|CONFIRMED                   |RESOLVED

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
not doing RISC-V.

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