[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #172 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Alexandre Oliva from comment #171)
> cool, now the only weirdness left WRT M and N is in 2.1.3.  did you just
> miss those, or are there other reasons why they can/should be like that?

i missed reviewing them. did a minor reorg.

1) illegal, attn and nop are special cases that, in all cases, the Phase 1 can
ignore.

2) one nop encoding had been missed: N=1,M=1 which is effectively named
"nop.immediate" and that has been added now

3) at Phase 2 a decision can be made to re-analyse M and N and if M=0,N=0 throw
an illegal instruction trap, otherwise for all other N,M it's a "nop".

4) there were some spare brownfield encodings which are 16bit mode only, enough
for two instructions that takes a nonzero register.  i decided to make these
mtcr and mfcr (moved into System section) and freed up some brownfield space
formerly taken up by those.

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