[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #151 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Alexandre Oliva from comment #147)
> in the pseudo code of phase 1, since we're talking about two separate insns,
> it would be desirable to make it explicit whether the Ms, Ns, and extc_id
> that appear there are taken from previ or from nexti.

agreed.

they are taken from the insn which is the current insn i.e. associated with
nexti.

this can be made clear, i feel, by creating a variable "curi = nexti" and
renaming insn to cur_insn


> I'm also missing code to handle previ.mode == v3.0B_then_16bit.  

yes.  i know i will get this wrong when not having actual code to execute with
unit tests so left it for now

> it's
> particularly important to specify how the conflict is resolved when nexti is
> a 10-bit insn: does the return-to-16-bit direction prevail over the M bit in
> nexti, or vice-versa, or is that conflict to be rejected?

don't know.

one school of thought would say "raise an illegal exception", another would say
"allow it", yet another would say, "use it as an escape-sequence of some kind".

i honestly have no idea which is best, except at the level of being not in
favour of complicating the Phase 1 FSM.

on that alone, "allow it" wins because even an illegal exception is extra
gates.

but... is that good? i don't know.  thoughts?

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