[Libre-soc-bugs] [Bug 469] Create D-cache from microwatt dcache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=469

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #12)
> Hi Luke, I'm struggling with translating the generate statements and
> generic/port maps, can you give me some feedback on whether the following is
> a correct translation? Thank you :)
> 
> ```dcache.vhdl
> -- Generate TLB PLRUs
> maybe_tlb_plrus: if TLB_NUM_WAYS > 1 generate
> begin
> tlb_plrus: for i in 0 to TLB_SET_SIZE - 1 generate
>     -- TLB PLRU interface
>     signal tlb_plru_acc    : std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
>     signal tlb_plru_acc_en : std_ulogic;
>     signal tlb_plru_out    : std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
> begin
> tlb_plru : entity work.plru
>     generic map (
>         BITS => TLB_WAY_BITS
>         )

tlb_plru = Plru(TLB_WAY_BITS)

>     port map (
>         clk => clk,
>         rst => rst,
>         acc => tlb_plru_acc,
>         acc_en => tlb_plru_acc_en,
>         lru => tlb_plru_out
>         );

comb += tlb_plru.acc.eq(tlb_plru_acc)
..
comb += tlb_plru_out.eq(tlb_plru.lru)

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