[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #65 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #64)

> 
>   2. Its the interface *for now* and it will change in the future to
>      some normalized standard.

the wishbone interfaces will be connected internally to a bus.  on that bus
will be peripherals.  the peripherals will be connected to IO pads.

the wishbone bus itself will *not* be exposed via IO pads.

>   If its the second case, to have a better approximation, we must keep
>   the wishbone interface exported for now.
> 
> 
> > we still have to fit a set of GPIO and i am currently sorting out Litex SIM
> > to be able to at least have something even if it is utterly basic.
> 
>   OK.
> 
>   Some update from my side, I'm implementing a high fanout net synthesis
>   algorithm which is roughly placement driven.

nice.

> As I'm experimenting
>   various ways as I go, I do not commit because of very ephemeral
>   stages.
>     I'm also working with Staf on the TSMC 180nm portage to Coriolis.

ah good.

>     And, I'm (again) in vacation until Sunday 6, September, so the
>   advance of the work will depend on the (bad) weather...

not enough sun last time? :)

>     By the way, the port 922 is filtered by the ISP of my current
>   accommodation so I get them though my home box (after transforming
>   the commits into patches). Writing this make me think I should
>   have just made a ssh tunnel. Stupid of me.

doh.

do you have a friend or colleague who can make one?

or, you know, there is only one file changed, test_issuer.il it can be got by
the git.libre-soc.org website.

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