[Libre-soc-bugs] [Bug 469] Create D-cache from microwatt dcache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=469

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
#     subtype way_t is integer range 0 to NUM_WAYS-1;


therefore wherever you *see* way_t, replace it with "NUM_WAYS".

#         hit_way   : way_t;

                self.hit_way   = Signal(WAY)

no - this needs to be:

                self.hit_way   = Signal(NUM_WAYS)

likewise:

#         forward_row1   : row_t;

                self.forward_row1     = Signal(ROW)

no - look at the definition of row_t:

#     subtype row_t is integer range 0 to BRAM_ROWS-1;

therefore that needs to be:

                self.forward_row1     = Signal(BRAM_ROWS)

etc. etc.  exactly the same for INDEX, and probably CACHE_TAG as well.

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