[Libre-soc-bugs] [Bug 450] Create MMU from microwatt mmu.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=450

--- Comment #64 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #58)
> Done all the other comments/fixes :)

#               v.pgbase := pgtbl(55 downto 8) & x"00";
                # set v.shift to rts so that we can use finalmask
                # for the segment check
                comb += v.shift.eq(rts)
                comb += v.mask_size.eq(mbits[0:5])
                comb += v.pgbase.eq(pgtbl[8:56])

note that i said, "at the *end*".

> also: wherever there is an eq into a full Signal (*not* a slice), AND THE
> LAST Cat IS ZEROS

if they are at the start, they are LSBs.  therefore, by removing them, the
assignment has shifted in this case by 8 bits.

commit 9af0f3f969658fe7b9903a134e0bfe52ddcb8631 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Sun Aug 16 10:21:09 2020 +0100

    restore incorrect removal of zero-Cat at LHS (should never do that)

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