[Libre-soc-bugs] [Bug 450] Create MMU from microwatt mmu.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=450

--- Comment #30 from Cole Poirier <colepoirier at gmail.com> ---
Several questions:

How do I specify a signal as a non-zero positive integer in nmigen? in vhdl
it's specified with the keyword 'positive'.


How should the assignment of a a value to a variable with the representation
"(others => '0')" in vhdl, *outside* of a case statement, be translated into
nmieng?

For example:
```
tlb_data := (others => '0')
```

Is this translated correctly? i.e. the number of bits in a hex constant?
```
#       -- mask_count has to be >= 5
#       m := x"001f";
# mask_count has to be >= 5
# TODO check hex conts with lkcl
comb += mask.eq(Const(0x001F, 5)
```

Is this correct? If a statement X is wrapped in an or in vhdl, in nmigen it is 
or'd with 0? i.e. 0 | X?

```
# nonzero := or(r.addr(61 downto 31) and
#            not finalmask(30 downto 0));
# TODO need lkcl to check this is correct
comb += nonzero.eq(0 | Cat((~finalmask[0:31]),
                   r.addr[31:62]
                  ))
```

How do I start testing/getting this module to work? Should I just move on to
translating icache.vhdl(~800 lines), d.cache.vhdl(~1600 lines), etc. because
their incredibly tight integration with mmu.vhdl means that I should work
concurrently on making them 'run' (work all of them together once they have all
been translated 99%)?

Also should AddrShifter, MaskGen, etc. classes be made submodules of MMU?

Am I corectly initing things, and inheriting in nmigen in a way that properly
corresponds to the vhdl, or even correct in terms of general python?

I know this is a lot of questions, but I'm unsure as to how I should progress
from here, as I know I'm doing things wrong, but I don't know what specifically
I have done wrong. My plan as of this moment is to start translating
icache.vhdl into nmigen tomorrow.

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