[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #61 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #58)
> (In reply to Jean-Paul.Chaput from comment #57)
> > (In reply to Luke Kenneth Casson Leighton from comment #55)

> what i would like, there, is wildcard matching e.g. starts with "oper_i" or
> ends with "_ok" and the pincount to be obtained from the object.
> 
> this will reduce 30-40 lines per block down to *five* and at the same time
> greatly increase clarity.

  I will keep that in mind and try an implementation when I find time.


> > I also removed the utils module, as now Coriolis should supply equivalent
> > features.
> 
> ah excellent, glad you liked it.
> 
> Config is neat, ehn? :)

  Yes. I did upgrade my Python knowledge here... Always the dilemma
  of whether taking time to properly learn or develop using what I
  already master. I suppose I'm still missing lots of features.


> the number of oper_* pins is far too large.  this is the "expansion" of the
> instruction for convenience.  an example is the 64 bit immediate.
> 
> basically i am going to have to do "subset instruction decoders" that are
> *inside* mul0, *inside* alu0 and so on.
> 
> i have to find time to do that.

  For a floorplanned approach, reducing the number of wires between
  blocks is very important. But it is almost an art...

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