[Libre-soc-bugs] [Bug 450] Create MMU from microwatt mmu.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=450

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
delete this entire block and de-indent the if else.

nmigen automatically handles reset with an argument "reset=x" to Signal
constructor which defaults to zero.

given that all the values here are zero the entire block, including rst and
including the if else is totally unnecessary.



 199             with m.If(rst == 1):
 200 #               r.state <= IDLE;
 201 #               r.valid <= '0';
 202 #               r.pt0_valid <= '0';
 203 #               r.pt3_valid <= '0';
 204 #               r.prtbl <= (others => '0');
 205                 sync += r.state.eq(State.IDLE)
 206                 sync += r.valid.eq(0)
 207                 sync += r.pt0_valid.eq(0)
 208                 sync += r.pt3_valid.eq(0)
 209                 # TODO value should be vhdl (others => '0') in nmigen
 210                 sync += r.prtbl.eq(0)
 211 #           else

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