[Libre-soc-bugs] [Bug 449] FU unit tests checking output one cycle too late

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=449

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Blocks|                            |324
         Resolution|---                         |FIXED
             Status|CONFIRMED                   |RESOLVED

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #0)
> I finally figured out why the div pipe was failing with the FSM:
> the unit test was checking the output one cycle later than it should. 

hmmm yeah i found timing issues with MUL as well, these unit tests
are cobbled together to do manual ready/valid signalling which is
normally handled by the CompUnit "Manager".

> Once I fixed that, the tests pass for all three div pipe implementations.

excellent.

> The unit tests for the other FUs are probably broken in the same way, so I'm
> creating this bug report to track fixing it.

i ran test_div_compunit.py and it worked perfectly: i expected that it would.

with each test_pipe_caller.py being hand-written ready/valid signalling,
it's kiinda "ok" that their ready/valid signalling is "borked" (or in
the case of the single-stage ones such as ALU and Logical, *completely*
borked).

as long as the test_*_compunit.py functions correctly it's fine.

this is precisely why we have unit tests at every integration level.

i think we're good on this one.


Referenced Bugs:

https://bugs.libre-soc.org/show_bug.cgi?id=324
[Bug 324] create POWER DIV pipeline
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