[Libre-soc-bugs] [Bug 340] formal proof of POWER9 SHIFTROT pipeline needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=340

--- Comment #16 from Samuel A. Falvo II <kc5tja at arrl.net> ---
Created attachment 95
  --> https://bugs.libre-soc.org/attachment.cgi?id=95&action=edit
Screenshot showing failure mode of shiftrot pipeline.

In this screenshot, you can see GTKWave's output for the failing case.  Note
that MB < ME, which means that ml & mr should yield a non-zero mask.  ml should
have the lower 16 bits set.  mr should have the top-most 20 bits set.  Instead,
ml=0, and mr=0xFFFFFFFF.

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