[libre-riscv-dev] PPC on Talos and Playstation 3

[Luke Kenneth Casson Leighton]

On Mon, Mar 30, 2020 at 7:57 PM Immanuel, Yehowshua U
<yimmanuel3 at gatech.edu> wrote:
>
> > yehowshua, you're aware that by choosing to do this, that you'll be
> > committing over 6 months of your life to the task?  that's typically
> > how long it takes (if not longer).
>
> Oh wow! Why so long

https://git.libre-riscv.org/?p=ieee754fpu.git;a=shortlog;pg=19
then page back and watch the months go by.

> - I was thinking maybe 4 weeks…

no chance.  we started in february, last year, working from jon
dawson's verilog code and hand-converting it to nmigen.  we were
delighted when, a week later, we had working IEEE754 FP add.

by around 2 months we had MUL and a decent pipeline structure.  at
some point i worked out how to parameterise the code.

at least 6 weeks were spent writing unit tests.

FPDIV took about 2 months: Jacob wrote some code that does div *and*
sqrt *and* rsqrt, that was about 5 weeks i think?  then it took me
about 3 weeks to join it together into FP (jacob's code was
fixed-integer).

then i added integer to fp and fp to integer, and class and FCVT,
those all took around... 2 and a half weeks i think, including unit
tests.

michael recently did FPMAX, FPCMP etc. which was... about a week.

we still have to do SIN, COS, ATAN2, ROOT3, POW, LOG, LOG1P, ACOS and
more.  this will be about another 2 months.


> At a minimum, I’d like to at least see how well Bluespec handles FPU configuration.

great - just remember that we're under time pressure and so anything
that means "team has to learn a new language which is KNOWN to cause
massive problems due to its insanely high barrier to entry" has to be
excluded from going into the ASIC.

> The maintainer of BSC has been quite helpful in general - so I should him or her just how flexible is BSC for specifying an FPU…

is that Niraj?  he's really good.

l.