[libre-riscv-dev] PPC on Talos and Playstation 3
programmerjake at gmail.com
Mon Mar 30 20:01:42 BST 2020
On Mon, Mar 30, 2020, 11:36 Immanuel, Yehowshua U <yimmanuel3 at gatech.edu>
> Before I try my hand at an FPU,
> Some questions:
> - Do we have any FPU attempt in nMigen, Verilog, or some other language
> yet that I should be aware of?
- The POWER ISA 3.0 PDF doc specifies an IEEE 745-1985 compliant mode as
> well as a faster non-compliant mode - I’m guessing we have to implement
I was assuming we'd just implement them both as fully IEEE 754 compliant,
unless the noncompliant mode mandates something incompatible with IEEE 754
such as flushing denormals to zero.
- I imagine your RUST algebraics library should be useful for this?
Assuming you mean simple-soft-float, since algebraics is basically a exact
real number arithmetic library rather than a IEEE 754 library.
I hope so, i'm currently adding support for power-specific status flags and
proper NaN payload propagation, which are the last two things needed to be
fully Power compliant (assuming no bugs). It is currently RISC-V compliant
since RISC-V doesn't have extra status flags or NaN payload propagation.
- how many stages should I have for the FPU - is there a sweetspot?
for add/sub/mul, somewhere around 3 or 4, for div/sqrt/recip-sqrt more is
ok, maybe 8-10?
- We’re doing a reconfigureable FPU correct? What bit modes does it
4x16-bit, 2x32-bit, 64-bit. We're planning on having 2 64-bit units. The
FPU should be designed to reuse the reconfigurable integer multiplier since
that's most of the logic in fpmul or fma.
Also, the FP divider should also be shared with integer div/rem. For a
working pipelined integer/fixed-point div/rem/sqrt/recip-sqrt unit, see:
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