[libre-riscv-dev] PPC on Talos and Playstation 3

[Luke Kenneth Casson Leighton]

On Mon, Mar 30, 2020 at 7:35 PM Immanuel, Yehowshua U
<yimmanuel3 at gatech.edu> wrote:

> Before I try my hand at an FPU,

yehowshua, you're aware that by choosing to do this, that you'll be
committing over 6 months of your life to the task?  that's typically
how long it takes (if not longer).

> Some questions:
>  - Do we have any FPU attempt in nMigen, Verilog, or some other language yet that I should be aware of?
>  - The POWER ISA 3.0 PDF doc specifies an IEEE 745-1985 compliant mode as well as a faster non-compliant mode - I’m guessing we have to implement both?

sigh.  probably.

>  - how many stages should I have for the FPU - is there a sweetspot?

we have a trade-off between maximum clock rate and the number of
Function Units (Reservation Stations) needed.  so if there are 16-long
pipelines, then that *REQUIRES* 16 Function Units, in order to keep
them fully occupied and still be able to re-associate the result with
the correct FU when it comes back out the pipeline.

if the number of FUs increases too much, we have a problem with the
size of the Dependency Matrices.

i really do not want to go above around 20 FUs.  that's still pushing it.

* 6 to 8 of those will be LOAD/STORE.
* at least 2 will be Branch.
* at least 2 will be for predication.

this only leaves 8 (EIGHT!) for ALU operations, which in turn means
that pipelines really cannot go about 8 stages, and that we cannot
have separate FP and INT Function Units.


>  - We’re doing a reconfigureable FPU correct? What bit modes does it support?

literally anything.  it's defined in a single python dictionary, with
the mantissa and exponent being specified as parameters, by way of a
lookup (the bitwidth) as the key of the python dictionary.

one line of code.

l.