[libre-riscv-dev] cache SRAM organisation

[Lauri Kasanen]

On Fri, 27 Mar 2020 09:44:30 +0000
Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:

> when bypass latches are open and we run at 800mhz:
>
> * actual speed: 800 mhz
> * stages: 10 (double)
> * latency (completion time): 1.25e-9 times *10* = 1.25e-8 *HALF THE LATENCY*

Sorry, but isn't that double the latency?

- Lauri