[libre-riscv-dev] cache SRAM organisation

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Mar 27 09:16:15 GMT 2020

On Fri, Mar 27, 2020 at 9:09 AM Staf Verhaegen <staf at fibraservi.eu> wrote:

> I still feel you intermix synchronous and write-through in this statement, the above seems to be possible with synchronous SRAMs.

this would be good.  what would help clarify immensely is if you could
let us know what options to nmigen Memory class are "supported".
then it is really clear.



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