[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #126 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
here's ppc_update_cr0:

https://github.com/sebastianbiallas/pearpc/blob/master/src/cpu/cpu_generic/ppc_opc.h#L26

#define CR_CR0_LT (1<<31)
#define CR_CR0_GT (1<<30)
#define CR_CR0_EQ (1<<29)
#define CR_CR0_SO (1<<28)

* clears the CR-CR0 bits
* result is zero: sets bit 29
* result top bit is set (indicating -ve as signed): sets bit 31
* otherwise (+ve signed): sets bit 30
* after that (in *addition*): if the XER SO bit was set, set bit 28 of CR0

interestingly, then, it looks like you have to check the XER flag *before*
checking the carry.  and XER is set based on... err... comparing operand A
with the result.  how odd.
https://github.com/sebastianbiallas/pearpc/blob/master/src/cpu/cpu_generic/ppc_alu.cc#L86

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