[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Thu Mar 26 17:15:44 GMT 2020


--- Comment #124 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #122)

> how many bits is that
> 0x 1 0000 0000 0000 4444
> ha, that's amusing.  the result is a roll-over from 64-bit arithmetic
> > Need to sort out setting the carry and overflow flags at some
> > point though, that'll be more fun...
> yehyeh.  a SPR storing the carry, first.  take a look at pearpc,
> it should show a way to do it (that's easy to interpret)
> https://github.com/sebastianbiallas/pearpc

Ooops, some of my experiments with carry must have snuck in, sorry. Speaking
of, I'm getting some weird behavior with carry on qemu. If I run some
instructions that generate a carry or overflow, then have gdb read the xer
register, it returns 0. But if I execute a `mfxer r5` or the like and print out
that register, it gives me the correct value for xer. I'm trying to confirm
whether this is a bug with qemu or not.

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