[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=257

--- Comment #18 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
oh.  one important thing that came out of the discussion on comp.arch:
the number of wires involved, if we are not careful, is MENTAL.

let's imagine we pass the expanded (shifted, masked) data and op-length
out from each FunctionUnit.  the data, previously a maximum of 64 bit,
is now a full cache-line wide (because it has been shifted into position
for the cache write), and the operation, previously encoded as len=1,2,4,8
(we could use 2 bits for that) and in binary address form LSBs 0-3, is
now a 16 bit mask...

oh times two, one for the aligned and one for the misaligned LD/ST.

so that's 128, 256, plus 16x2=32 equals 288 wires per LD/ST FU, of which
there will be 8.

that's a staggering 2,304 wires *just for the data*

eep.

if we do the splitting *after* the Muxing through the 4-port Muxer(s),
*even if the splitting was needed for input into the Address Clash Matrix*,
we can halve that number of wires to "only" around 1120.

kiinda important :)

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