[libre-riscv-dev] cache SRAM organisation

Staf Verhaegen staf at fibraservi.eu
Thu Mar 26 12:31:38 GMT 2020

(Sorry send to early)

> .In theory on a single port SRAM

In theory on a single port SRAM the write data input and the Q data output could be on opposite sides of the block but I will make sure that these pins are on the same side of the block and close together so you don't need much wire to connect a pass-through MUX.


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