[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #114 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
actually, i like what you wrote a whooole lot better, michael:
https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/soc/simulator/qemu.py;h=c9b1b573dd22d3da0adb0415a0a6b8bb005c99c6;hb=4b50a170c413f47e0527c843be49babc493c684b

the only modification i needed:

set architecture powerpc:common64
target remote localhost:1234
layout asm
b *0x20000000
c

and to use debian package "gdb-multilib" which *sigh* had to come from
debian/unstable.

building cross-compilers etc. from source has always stressed me out :)

if we do that, we need a proper documented reproducible process.

how did you get powerpc64-linux-gnu-gdb?

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