[libre-riscv-dev] cache SRAM organisation

[Jacob Lifshay]

On Wed, Mar 25, 2020, 08:54 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Wed, Mar 25, 2020 at 1:46 PM Staf Verhaegen <staf at fibraservi.eu> wrote:
>
> > Keep the discussion on development of other types til after the
> prototype tape-out in October.
>
> good idea.
>
> > I know there is other development ongoing for dual port RAM in the
> OpenRAM community so likely it is more clear what extra still has to happen.
> > BTW, I think there also is possibility to have register files block with
> 2R1W RAM blocks.
>
> ah that's good.  we can combine two of them to create 4R1W (we need
> minimum 3R1W, however the design does not critically depend on this:
> it just takes 2 cycles to read all operands for 3-operand instructions
> such as FMAC).
>
> > > this because it turns out that asynchronous SRAM can act, when used in
> aRegister File, as if it was a (separate) Register Bypass /
> ForwardingPort.  with the Out-of-Order Engine being a huge cyclic feedback
> loopbetween ALUs and RegFile, clock delays are an impediment, and
> havingcompletely separate (extra) Regfile Bypass ports dramatically
> increases thenumber of wires and Multiplexers.
> >
> > Could detail more on how the adress, data and output signals of this
> asynchronous block would be used and switched between synchronous and
> asynchronous functioning. To me it seems that it would just place of the
> multiplexers, not the amount.
>
> ok i will try to outine it, there is quite a lot of detail, i apologise.
>
> it's basically the "pass-through" system used in nmigen FIFOs, and the
> "synchronous" mode of nmigen Memory.  the requirements are: what is
> written has to be available *combinatorially* - i.e. on the same clock
> cycle - if simultaneously read via another port.
>
> now, yes i took note that this is not supposed to be permitted: you're
> not normally permitted to be able to read *and* write to an SRAM cell
> at the same time.  however, that's exactly what we need.
>

It seems obvious to me that you just add a mux on each read port to bypass
directly from the write ports when the address matches -- that way you
don't have to worry about needing both read and write to the same cell.

Also, assuming I'm not missing something, grouping two 1R or 1W srams
doesn't give 2R1W, it gives 2R or 1W since each cycle that you write, you
write to all srams meaning all srams can't read.

Jacob

>