[libre-riscv-dev] cache SRAM organisation

Staf Verhaegen staf at fibraservi.eu
Wed Mar 25 13:46:38 GMT 2020

Luke Kenneth Casson Leighton schreef op wo 25-03-2020 om 12:33 [+0000]:
> On Wednesday, March 25, 2020, Staf Verhaegen <staf at fibraservi.eu> wrote:
> > A single port SRAM has one port where you can do a read or a write eachclock cycle. The 2-port one has one read port and one write port so you cando a read and write each clock cycle. The dual port one now has two portsthat each can do a read or write each clock cycle. So you can do two reads,two write or a read+write each clock cycle.For each of them you can have a synchronous or an asynchronous version. Asynchronous RAM has a clock input and the address and data inputs arelatched on that clock signal. It thus means that the FFs are integrated inthe SRAM, e.g. thus very close :) . The RAM currently being developed in myNLNet project is a synchronous SRAM as this is easier from timing point ofview because all the timing can be related to the clock. A synchronous RAMactually functions as an addressable bunch of FFs and the synthesis and P&Rtools know how to handle them.
> ok.  later, we will definitely need an aysynchronous version.

Keep the discussion on development of other types til after the prototype tape-out in October. I know there is other development ongoing for dual port RAM in the OpenRAM community so likely it is more clear what extra still has to happen.
BTW, I think there also is possibility to have register files block with 2R1W RAM blocks.

> this because it turns out that asynchronous SRAM can act, when used in aRegister File, as if it was a (separate) Register Bypass / ForwardingPort.  with the Out-of-Order Engine being a huge cyclic feedback loopbetween ALUs and RegFile, clock delays are an impediment, and havingcompletely separate (extra) Regfile Bypass ports dramatically increases thenumber of wires and Multiplexers.

Could detail more on how the adress, data and output signals of this asynchronous block would be used and switched between synchronous and asynchronous functioning. To me it seems that it would just place of the multiplexers, not the amount.


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