[libre-riscv-dev] cache SRAM organisation

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Mar 24 22:32:52 GMT 2020


Staf can i ask you the favour of reviewing Mitch's comments about cache

in particular the comments about the possibility of using multiported SRAM
cells as long as only 1R or 1W is done on any given cell?

also something about doing the FFs yourself, close to the SRAM cells?


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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