[libre-riscv-dev] cache SRAM organisation

[Luke Kenneth Casson Leighton]

https://groups.google.com/d/msg/comp.arch/cbGAlcCjiZE/mgMZVINVIAAJ

Staf can i ask you the favour of reviewing Mitch's comments about cache
design?

in particular the comments about the possibility of using multiported SRAM
cells as long as only 1R or 1W is done on any given cell?

also something about doing the FFs yourself, close to the SRAM cells?

l.



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