[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Tue Mar 24 14:24:22 GMT 2020


--- Comment #22 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
another couple of pieces of code which need "parameterisation":

L1cache.v and Lxcache.v - the cache-coherence protocol used there
looks particularly good, and it would be nice to be able to see
this code in nmigen

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