[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Tue Mar 24 13:55:22 GMT 2020


--- Comment #15 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---

i wonder... i wonder if it would work if we had multiple L1 caches,
with an N-way crossbar on each (routing to be organised by binary
address bits [4:4+log2(N)-1]) then have a L2 cache underneath that?

or, just actually have multiple L1 caches with a coherent L2 cache

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