[libre-riscv-dev] Advanced Topics on RISCV

Jean-Paul Chaput Jean-Paul.Chaput at lip6.fr
Tue Mar 24 13:08:33 GMT 2020

On Tue, 2020-03-24 at 13:00 +0000, Immanuel, Yehowshua U wrote:
> > You can see details here:
> > https://www-soc.lip6.fr/trac/tsar
> Thanks, I see that it scales up to 1024 - that's fantastic.

  Yes. Even above that. We did use free tools for the HDL,
  but unusual ones. So maybe you should concentrate on the
  theoretical mechanisms and avoid banging your head on the
  tools themselves. The prototype, If I remember correctly
  is made in 28nm with on MIPS32 processors.
    The chip was implemented with Cadence however. But the
  HDL models are free.
    We have run NetBSD and Linux on it.


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      /v\     Jean-Paul.Chaput at lip6.fr
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    U P M C   Universite Pierre & Marie Curie
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    S o C     System On Chip

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