[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #96 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #95)

> yes.  however adding a power frontend on it as we found ain't so bad.  can
> use the same code.
> 
> if you look here you can see how basic the test simulator is
> https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/soc/experiment/score6600.
> py;h=babce2439233f84c262c08795b873a6167197ec9;hb=HEAD#l859
> 
> adjusting that so it uses InternalOp is... er... not hard? :)

Luke, looks like you and I are doing different things...? It looks to me like
score6600 is actual hardware, not a simulator. I have basic simulator I'm
working on here
https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/soc/simulator/internalop_sim.py;h=813dd19c40e21283d000fd597074a2cb38595a8a;hb=e95b4372c5163bb6f753c92d8445d4af7f117457
- I took some of the elements from score6600 (like the register and memory
file) and modified them to get a basic simulator, which I'm testing along side
a real power machine. Were you going for something different...?

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