[libre-riscv-dev] [Bug 264] ISA switch needs to be a privileged operation

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=264

--- Comment #11 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #8)
> (In reply to Luke Kenneth Casson Leighton from comment #6)
> > (In reply to Jacob Lifshay from comment #5)
> > 
> > > If we use the same 2 C opcodes for compressed pairs, then we can end up with
> > > 13.5 bits available per instruction, rather than just 11, which allows us to
> > > define about 5.656 (!) times as many compressed instructions.
> > > 
> > > 13.5 = (32 - 6 + 1) / 2
> > > 11 = 16 - 6 + 1
> > > 5.656... = 2 ^ (13.5 - 11)
> > 
> > other ideas along this theme include saying, in that initial 32-bit space,
> > is to specify how many of the next instructions are to be encoded as C.
> > 
> > i'd recommend to reserve the option to do this, as it involves storing state
> > (the countdown timer) whereas just having 2 C opcodes as pairs is dead
> > simple, as long as you accept that the PC encodes the state information
> > about the fact that if the PC is on a 2-byte boundary you're in the middle
> > of the pair.
> > 
> > this allows the PC to store the state if there is a trap.
> 
> Except, like I mentioned before, using the PC to store that info makes it
> ambiguous between executing the second instruction in a pair and executing a
> non-paired instruction that happens to start at a 2-byte boundary because
> there was a preceding 48-bit instruction.

*click* yes got it now.  ok so a bit (a "length of number of C instructions to
be decoded" where that length happens to be 1, is a solution there.

> So, we'll either have to not have
> any 48-bit instructions, not trap in the middle of a pair, or not have
> paired instructions.

storing an extra bit (or bits) in a SPR - particularly one that already has to
be saved - isn't so onerous.

> Switching instruction memory to always be in BE mode is not a good solution
> since that is not compatible with standard Power code that doesn't know
> about the endian switch.

well, luckily, if we accept the C-pair idea has to have at least a length of "1
bit" and that is stored in a context-switched SPR, it's ok.

later the length can be extended to say 3 or 4 bits.  or, heck, we might as
well just allow 3-4 bits anyway.

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