[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #84 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #83)
> (In reply to Luke Kenneth Casson Leighton from comment #81)
> > https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/soc/decoder/
> > power_fieldsn.py;h=a5e03a114ec54d915deb13f20c99e8ab59078dc5;hb=HEAD#l31
> > 
> > try subtracting start and end from from len-1, and sign inverting step, at
> > line 31
> 
> It's giving a key error because the index (31) isn't in the "dict" (I
> printed out the object and it gave SignalBitRange([(0, 31)]), and I assume
> it treats that as {0: 31}).
> 
> What's the purpose of line 1?
>                 k = OrderedDict.__getitem__(self, t)
>   

gets the remapping of what bit you want in the field onto what ACTUAL bit you
want in the instruction.


              res.append(self.signal[k]) # reverse-order here
> I think it'd work ok if I just grabbed the bit from the signal directly,
> like so:
>                 res.append(self.signal[t])

nope.

that will get you bit 0 of the instruction when you request bit 0 ofa **FIELD**
in the instruction.

so, apologies it was reverse the order of t not k

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