[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Wed Mar 18 21:23:43 GMT 2020


--- Comment #80 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
rright.  ok.  so i think, to "fix" thus, in SignalBitRange, the slice indices -
start, end (and direction) all need to be reversed *as well*.


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