[libre-riscv-dev] next tasks

Immanuel, Yehowshua U yimmanuel3 at gatech.edu
Mon Mar 16 18:30:15 GMT 2020

If we decide we don't want rpython, then I would suggest Rust — I’ve

Like I’ve mentioned before, I’m all for Rust.
If I remember correctly, we’re implementing POWER 3.0 and Gem5 only has support for 2.7(2.7 and 3.0 - wow sounds like Python versions :)…

Anyways, one thing we should strongly consider making the simulator take advantage of multiple cores.

Honestly, we could implement a single cycle CPU in RTL and the compile it into C++ with Verilator.
To me, this seems to be the way to go.

1. Verilator Creates quite speedy cycle accurate C++ models
2. RTL is a really natural way to describe a CPU - duh
3. A single cycle CPU is about 3 - 4 days worth of labor
4. If we did the Single cycle CPU reference simulator in BSV for example, it’d simulate even faster than it would in verilator

I know using an RTL implementation of a CPU to test other RTL implementations seems unatural, but if we’d want to catch errors like pipeline and flushing behaviors in our CPU, then what makes more sense than a single cycle reference?

Also, I’d imagine in the future that we’d want to have speedy unit-testing etc etc, and considering ventilator offers multi-core support, we could see the speedup benefit of throwing our unit tests at a 64 core risen 3990x for example.

@Lauri, Jacob, and Luke - Thoughts and Comments?


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