[libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun Mar 15 19:56:30 GMT 2020

On Sun, Mar 15, 2020 at 7:44 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
> On Sun, Mar 15, 2020, 12:33 Immanuel, Yehowshua U <yimmanuel3 at gatech.edu>
> wrote:
> > Who knows, I could be wrong. Maybe people really would find a use for dual
> > ISAs - but up front, to investor for example, and to me, it looks
> > unnecessary.
> In my opinion, dual ISAs is a significant advantage that basically no one
> else has, since it allows us to run both Power and RISC-V software at full
> speed, it's also useful for on a test server where people need to test both
> Power and RISC-V software (where QEMU isn't good enough).

from a commercial perspective, given that there doesn't exist any
mass-volume products that use RISC-V (just a lot of noise and a lot of
talk), it's not as attractive as it seems.

if however we assume that RISC-V *will* take off in mass-volume,
*then* it might become attractive.

however given that the RISC-V Foundation's reputation is now shot to
shit, and people know - loud and clear - that they are "Fake Open
Source", i highly doubt whether mass-commercial
*end-user-programmable* RISC-V systems will actually take off any time
in the next 8 to 12 years.

> Later (for Libre-SOC v2 or v3), it might be a good idea to add support for
> x86 and x86_64 user-mode since the patents for the base ISA will have
> expired by then. This would help give us an advantage since it would allow
> us to run legacy software.

now that *would* be good.

as we saw with the China ICT "Loongson G" architecture, even just the
base ISA having *partial* x86 hardware ISA support would give a
massive speed-boost of an emulated application.


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