[libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility

[Immanuel, Yehowshua U]

> no it doesn't, at all.  here's the ISA tables:
> https://libre-riscv.org/openpower/isatables/

So RISCV is ONLY in software at this point - that is no RISCV on the actual hardware?

And I know I seem a little pushy - but I have to be able to justify RISCV support upfront.
To put it differently, if you can convince me of the value of retaining RISCV, then you can convince anyone.

Yehowshua