[libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility

[Jacob Lifshay]

On Sat, Mar 14, 2020, 21:01 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> 3) where is the port of softfloat-3 that supports POWER IEEE754 format?
>

You can use simple-soft-float which is (modulo possible bugs) entirely
correct for Power except that it might propagate NaN payloads incorrectly
since NaN payload propagation is only partially implemented and that it
needs to have the additional 20-30 lines of trivial code added to record
the cause for generating a NaN (because Power has more than the standard
list of FP exception conditions).

To operate on the Power f32-in-f64 format all you need to do is convert all
inputs to f32 (check manual for exact operation), do the operation in f32
format, then convert back to f64 (conversion is lossless).

Additional benefits include: not needing compile-time flag changes to
switch between Power and RISC-V modes (everything is dynamically
adjustable).

The code is written on top of the algebraic numbers library I wrote (gives
us a type that behaves like an infinite-precision real number) and in a
straight-forward manner (no fancy math to make it faster), hopefully making
the internal algorithms easier to prove correct (assuming the algebraics
library gives the correct answer).

There are tested Python bindings.

I did test it against softfloat3 for RISC-V, all tests pass.

source:
https://salsa.debian.org/Kazan-team/simple-soft-float

autogenerated Rust docs:
https://docs.rs/simple-soft-float/0.1.0/simple_soft_float/

Jacob

>