[libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility

Jacob Lifshay programmerjake at gmail.com
Sun Mar 15 03:17:07 GMT 2020

On Sat, Mar 14, 2020, 18:01 Immanuel, Yehowshua U <yimmanuel3 at gatech.edu>

> Hello Jacob,
>         I’m running through the numbers and studying LibreSOC’s potential
> markets, and how we’d market the dual architecture.
> Just how feasible is the dual architecture we’re currently embarking on.
> Luke says its doable.
> What are your thoughts, and what are the challenges - just trying to get a
> comprehensive understanding.

It will be quite easy to do from the hardware side due to the relative
simplicity of user-mode RV64GC -- basically all we need is to do is
implement the instruction decoder and clean up the odds and ends that
result from the semantic differences.

The software side will be a little harder but still relatively easy, we
need to implement support for translating Linux system calls from the
RISC-V interface to the internal calls, as well as implementing the
syscalls for switching modes between ISAs -- that's like 80% of the work on
the Linux Kernel side. For userspace, we can have just executing RISC-V ELF
executables as a MVP, later, we can implement the stuff in the dynamic
linker to handle having both Power and RV code loaded in the same process
-- I'm thinking we should use a system similar to Wine and Darling (like
Wine but macOS on Linux) where they have two dynamic linkers in the same
process. Will have to figure that out.

We can also build a bare-metal hypervisor-like program to emulate RV system
mode to allow easier testing (don't need to boot a whole Linux kernel) as
well as booting a whole RISC-V OS. I'd estimate that it would be less than
10kloc of code.


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