[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=241

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://github.com/CSL-KU/SpectreGuard/blob/master/gem5/src/arch/power/isa/formats/integer.isa

this looks reasonable to work with.  it is a code-generator. so the hardware
for-loop will go in as c code outputted as a c for-loop.

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