[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Fri Mar 13 20:16:34 GMT 2020


--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
here's some links to existing code:

the MemFunctionUnits:
this is the "top level" of the mem-matrices, so quite boring

still boring:

ok *now* we are cooking:

however this is really the key bit:

that is where you get a Pascal's Triangle of address-comparators
*only in the bottom 10 bits*.

the actual algorithm is described in Mitch's book chapters, 11.4.12
i'll attach screenshots for the diagrams in a second.

the code i would like to connect to is here:


and here is where the LOADs/STOREs actually get fired off:

here, rather than have that code *arbitrarily* fire off the LD/ST, and *assume*
it will complete in a single cycle:

* stwd_mem_o must be PREVENTED from asserting UNTIL it is absolutely known that
the store will succeed
* load_mem_o must likewise be prevented from asserting until the load is known
to succeed

thus, it is perfectly fine for LOAD (or STORE) to take more than one cycle
(just like any other Function Unit).

yes, i know, if the LD/ST cannot complete (raises an exception) this is a type
of "result", which must result in the cancellation of the instruction (and all
downstream instructions), and an exception raised.

this is TODO however it is important that the information propagate back
through the LOAD/STORE buffer as a potential "result": "LOAD could not take
place due to exception".

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