[libre-riscv-dev] [Bug 256] New: Enhancements to an OpenPOWER ISA-level Simulator are needed

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Fri Mar 13 18:26:47 GMT 2020


            Bug ID: 256
           Summary: Enhancements to an OpenPOWER ISA-level Simulator are
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

The vectorisation and other improvements needed for the LibreSOC need a
simulator in order to test out applications at the assembly-code / binary
level, prior to implementation in hardware.  An instruction-compatible
simulator will be able to execute programs at reasonable speed whereas the
hardware-level simulator will be hundreds of thousands of times slower.  gem5
is a suitable starting point, and the modifications to spike (RV simulator)
need to be ported to it:

see this:

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