[libre-riscv-dev] [Bug 240] New: POWER-RISCV ISA switch formal standard writeup needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=240

            Bug ID: 240
           Summary: POWER-RISCV ISA switch formal standard writeup needed
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

A formal write-up of the means by which processors may switch to RISC-V (and
back, from POWER), to be proposed to the OpenPOWER Foundation at a later date.

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