[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=217

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
so, jock, just a bit of background:

we have a *massive* class hierarchy (well over 250 class instances, all of
which need to be laid out), which will produce something like 500,000 gates,
which is far too much to do all in one go.

so we want to split down the "tree" of class instances into progressively
smaller blocks, not going completely mad about it, maybe two levels deep.  this
will mean that the number of class instances ("blocks") that need to be placed
*by hand* is  reduced down to maybe... 50 to 80.

the "top level" is called a "floor plan", and we need to best organise the
routing between all those "blocks", so that their inputs and outputs are all on
the "most efficient side".

the last thing we want, for example, is that to get the I/O to a particular
block, it has to go *all the way round* the outside of a block.

some of the data buses will be a whopping FOUR TO FIVE HUNDRED wires (or more),
which will be completely dominating the centre of the chip, branching out.

sometimes, for smaller blocks, we definitely want the wires to be evenly spread
out across the whole of the side of the block (just like in
benchs/nmigen/ALU16)

sometimes, we want a bus (address / data / control lines) to come in on a
*specific* location - the corner, or the middle - of a block, on one particular
side.

so this is what we need to be able to specify.


also, we need to ensure that the auto-router does *not* ignore the pads (which
will go on the very outer edge of each Block), and that means putting BLOCKAGEs
in, as "rings", around the outside of the Block.

jock: see /alliance-check-toolkit/benchs/nmigen/ALU16/doAlu16.py for an
example.

looking at class ChipConf: Jean-Paul, it is not clear whether ChipConf will
automatically create the full range of BLOCKAGEs nets.  i am grepping the
source code "self.corona" and there is no evidence of self.corona actually
being set!

ChipConf.findPowerAndClockNets() *uses* self.corona, however there's no
*setting* of self.corona!

what gives?

-- 
You are receiving this mail because:
You are on the CC list for the bug.